Built with Red Chili

Our IP, built with Red Chili

We use Red Chili and today’s coding agents to build real chip IP: a module library, two RISC-V CPUs, SoC IP, a microcontroller and an application SoC, and an edge AI accelerator. Each design proves Red Chili works on real chip design, and each is IP you can license.

more CoreMark per second than Ibex maxperf: +38%
higher clock than Ibex maxperf: +59%
of verified modules, from library to SoC: Hundreds

ChillU-S against Ibex maxperf, in the same ORFS flow on the same CoreMark binary. How we measured it

These numbers keep moving. Agents guided by Red Chili work on our IP continuously: profiling CoreMark, tightening timing and area, and re-verifying every change against the RISC-V reference models.

Built bottom-up

Each layer is built from the one below, and every layer is verified on its own.

L1
Base modules
flops, counters, FIFOs, synchronizers, arbiters
L2
Building blocks
pipelined multipliers, dividers, floating-point adders, AXI crossbars
L3
CPU and IP parts
instruction decoder, register file, UART transmitter, DMA channel
L4
IPs
RISC-V CPU, interrupt controller, UART, SPI flash controller, DMA
L5
SoC
a microcontroller: CPU, memories, bus fabric and peripherals

ChillU-S

Microcontroller CPU

ChillU-S is our compact microcontroller core: a three-stage RV32IMC pipeline aimed squarely at the best small cores in its class. Against Ibex maxperf, in the same ORFS flow on the same CoreMark binary, it runs 38% more CoreMark per second at a 59% higher clock.

RV32IMC with machine and user mode, Zicsr, Zifencei and Zicntr
Physical memory protection, interrupts and WFI with sleep clock gating
Optional two-way instruction cache of 2 or 4 KiB
RISC-V debug with hardware triggers
Matches Spike instruction by instruction over RVFI
Passes riscv-tests and the official RISC-V architectural tests against Sail
Taken from RTL to layout with OpenROAD-flow-scripts (ORFS)

ChillU-X

Application CPU

ChillU-X is our application-class core: a deeply pipelined, dual-issue RV64 core with virtual memory that runs Linux in ChiliSoC-X. With a plain ‑O2 build it runs 3.4 CoreMark/MHz, ahead of the leading commercial cores in its class.

RV64GC with bit manipulation (Zba, Zbb, Zbs, Zbc); machine, supervisor and user modes
Virtual memory with an MMU, ready for Linux
Dual issue on an eight-stage in-order pipeline
Two-level branch prediction: branch target buffer, return stack and gshare
L1 instruction and data caches inside the core, with an AXI4 port
Physical memory protection, memory attribute regions, RISC-V debug and triggers
Atomics and hardware performance counters
Matches Spike instruction by instruction over RVFI
Taken from RTL to layout with OpenROAD-flow-scripts (ORFS)

Module library

BaseChiliSV

The parameterized, synthesizable SystemVerilog library everything else is built from, from base modules to AMBA fabrics and floating-point units.

Base modules: flops, counters, FIFOs, synchronizers, arbiters, clock gating
Arithmetic: a pipelined 64-bit ALU with bit manipulation, pipelined and iterative multipliers and dividers, FP32 and FP8 units, block floating-point encoders and decoders
Cache building blocks: line memories, miss and eviction buffers, store buffers and AXI4 line fills
AMBA interface modules: AHB, APB and AXI managers, subordinates, fabric and bridges
A testbench with coverage minimums and invariant checkers for every module

SoC IP

ChiliMix SoC IP library

Peripherals, interrupt and management units with standard register maps that existing drivers already know.

Interrupt controllers and timers: PLIC and ACLINT, PWM timers and a watchdog
Connectivity: ns16550a UART, GPIO, SPI with execute-in-place, I2C
DMA and a RISC-V debug module with JTAG
An L2 cache and a DRAM port for application-class SoCs
Register maps generated into RTL, C headers, docs and checkers
Formal proofs and a tracked verification plan alongside simulation

SoC

ChiliSoC-S

A complete microcontroller around ChillU-S and ChiliMix: boot ROM, SRAMs, cached execute-in-place flash and DMA on an AHB matrix, with the peripherals on APB.

Runs Zephyr, and debugs with OpenOCD and GDB over JTAG
Bus fabric proven formally end to end
Seeded stress tests across interrupts, bus stalls and debugger traffic
Taken through layout, with gate-level simulation matching RTL

Application SoC

ChiliSoC-X

An application SoC around ChillU-X and ChiliMix: one AXI4 crossbar to an L2 cache and DRAM, the peripherals on APB, and a slot for accelerators such as ChiliMind.

Runs Linux, with multi-hart interrupt and timer units
Boots from SPI flash with execute-in-place, alongside I2C, timers and a watchdog
Debugs with OpenOCD and GDB over JTAG
An accelerator slot that hosts ChiliMind, with a control window, a memory port and interrupts

AI accelerator

ChiliMind

An edge AI accelerator built for where language models are heading: hybrid models that mix recurrent state with attention. Instead of a generic matrix engine, ChiliMind specializes in what makes these models fast on small devices.

Built for hybrid models that mix recurrent state with attention
Model state and context kept on chip, close to the compute
Precision chosen per model at run time
Follows model structures as they evolve, not tuned to one

How far each IP has been taken

The evidence behind each block, from simulation to layout.

IP	Simulation	Formal proofs	Layout (ORFS)	Gate-level simulation	Notes
BaseChiliSV	Yes	Not yet	Inside a larger design	Inside a larger design	Layout and gate level inside the cores and ChiliSoC-S
ChillU-S	Yes	Not yet	Yes	Inside a larger design	Lockstep with Spike, architectural tests; gate level inside ChiliSoC-S
ChillU-X	Yes	Not yet	Yes	Not yet	Lockstep with Spike
ChiliMix	Yes	Yes	Inside a larger design	Inside a larger design	Layout and gate level inside ChiliSoC-S
ChiliSoC-S	Yes	Yes	Yes	Yes	Zephyr, OpenOCD and GDB, seeded stress
ChiliSoC-X	Yes	Not yet	Not yet	Not yet	Bare-metal programs, CoreMark and JTAG debug
ChiliMind	Yes	Not yet	Not yet	Not yet	Bit-exact against an independent reference

Yes In the IP’s own repositoryInside a larger design Inside a larger designNot yet Not yet

See the evidence

What Red Chili keeps for every block

Intent: What the module does, its assumptions and constraints
Evidence: Lint, synthesis, simulation and conformance results
History: Versions, decisions and planned work
Links: Dependencies, checkers and the tests that cover it

Custom-engineered IP

The flexibility of custom design, with the speed and economics of reusable IP.

You specify the function, microarchitecture, interfaces and PPA targets. We build on our library and IP with the same brain and agents, and deliver a release you can integrate.

Discuss custom IP

Every release ships with

RTL
Documentation
The verification environment: testbenches, checkers and regressions
Verification results: coverage, proofs and conformance
Implementation results
Integration material

Built for agent-driven chip design

As chip design becomes agent-driven, Red Chili helps the engineering infrastructure evolve with it. We’re opening pilots for RTL and DV teams already using coding agents.

Request a Pilot