Evidence

How we measure what we publish

Every claim about our IP comes with its method: the flow, the configuration, the reference it is compared against, the version and the date.

CoreMark per second: +38% over Ibex maxperf

CoreMark iterations per second at each core’s shortest timing-clean clock period, with the same program binary on both cores.

Measured: CoreMark/MHz in simulation, multiplied by each core’s clock at its shortest timing-clean period (one over the period)
Program: CoreMark, 3 iterations, compiled once with GCC 13.2.0 for rv32im; both cores run the identical binary in the same Verilator testbench
Compiler flags: -O3 -funroll-all-loops -finline-limit=600 -falign-jumps=4 -falign-loops=4 -ffreestanding -fno-common: the best set we found for both cores
Reference core: Ibex maxperf configuration (single-cycle multiplier, branch target ALU, writeback stage), lowRISC/ibex commit af456e25
Cross-check: Ibex built with its own published flags reproduces its published CoreMark/MHz, so the testbench does not favour our core
ChillU-S version: 0.29.0, commit 88cf10c, three-stage pipeline
Date: 2026-10-15

The maximum frequency OpenROAD reports at each core’s shortest timing-clean period, both cores taken from RTL to layout in the same flow.

Flow: OpenROAD-flow-scripts (ORFS), Docker image openroad/orfs:26Q4-71-g9b26ff8ff, Yosys with the slang front end
Settings: Identical for both cores: one clock, the same core utilisation, 20% input / output delay on every port, typical corner
Method: Clock period swept down until timing no longer closes after routing; the shortest clean period is recorded
Reference core: Ibex maxperf, lowRISC/ibex commit af456e25, the same top-level ibex_top used in the CoreMark run
ChillU-S version: 0.29.0, commit 88cf10c
Date: 2026-10-15

CoreMark per MHz in simulation with the plain build any user would start from, not a tuned compiler recipe.

Measured: CoreMark/MHz in the Verilator testbench, checked instruction by instruction against Spike
Program: CoreMark, 3 iterations, with the stock EEMBC port layer, compiled with GCC 13.2.0 for rv64imac with bit manipulation, running from the core’s own L1 caches
Compiler flags: -O2 -ffreestanding -fno-common
Comparison: Published plain -O2 measurements of the leading commercial dual-issue in-order application cores
ChillU-X commit: 4280cba
Date: 2026-10-26

Every change is checked against the RISC-V reference models before it is merged.

Instruction by instruction: Every retired instruction is compared with Spike, the RISC-V reference simulator, over the RISC-V Formal Interface (RVFI)
Architectural tests: riscv-tests and the official riscv-arch-test suite, run through RISCOF against the Sail reference model
Stress: Random instruction sequences, and random wait states on the instruction and data buses
Invariants: Assertions bound into every unit, compiled into every simulation
Coverage: Line, branch, expression and toggle coverage per unit, plus functional coverage of forwarding, traps, CSRs and memory accesses

The peripherals are proven formally where it matters; the complete SoC runs real software and has been taken through layout.

Formal proofs: SymbiYosys proofs (k-induction) of each ChiliMix IP’s register block and invariants, tracked item by item in a verification plan
Testbenches: A self-checking testbench for every module, with line and toggle coverage minimums
SoC regression: 19 programs on ChiliSoC-S, from interrupts, sleep and user mode to SPI, I2C, DMA, CoreMark and a seeded stress test
Software: Zephyr samples and kernel tests under twister; OpenOCD and GDB over JTAG
SoC formal: The bus fabric is proven end to end, and the SoC top with the core and memories cut out
Layout: ChiliSoC-S taken through ORFS, and gate-level simulation that matches RTL cycle for cycle on the programs run at gate level

Three independent sources must agree before an operation counts as done.

Contract: Each operation is defined bit for bit, with canonical vectors derived by hand
Reference: An independent integer reference, written from the contract text in NumPy only, tested against the vectors
RTL: Testbenches replay fixtures generated from the reference, with random stalls, and must match bit for bit

IP	Simulation	Formal proofs	Layout (ORFS)	Gate-level simulation	Notes
BaseChiliSV	Yes	Not yet	Inside a larger design	Inside a larger design	Layout and gate level inside the cores and ChiliSoC-S
ChillU-S	Yes	Not yet	Yes	Inside a larger design	Lockstep with Spike, architectural tests; gate level inside ChiliSoC-S
ChillU-X	Yes	Not yet	Yes	Not yet	Lockstep with Spike
ChiliMix	Yes	Yes	Inside a larger design	Inside a larger design	Layout and gate level inside ChiliSoC-S
ChiliSoC-S	Yes	Yes	Yes	Yes	Zephyr, OpenOCD and GDB, seeded stress
ChiliSoC-X	Yes	Not yet	Not yet	Not yet	Bare-metal programs, CoreMark and JTAG debug
ChiliMind	Yes	Not yet	Not yet	Not yet	Bit-exact against an independent reference

Yes In the IP’s own repositoryInside a larger design Inside a larger designNot yet Not yet

As of 2026-10-18. These numbers move as agents keep improving the IP; this page moves with them.